1. Field of the Invention
The present invention generally relates to the management of NAND flash memory, and more particularly to a caching device for NAND flash translation layer of the NAND flash memory.
2. The Prior Arts
Flash memories are commonly found in computers and consumer electronic products. For example, USB disks and MP3 players are the two most common applications of the flash memories. Among various types of flash memories, the NAND flash memories are commonly found in embedded systems. A NAND flash memory is organized into fixed-size pages (for example 512 bytes per page) and a number of pages constitute a block (for example 32 pages per block). A characteristic of the NAND flash memory is that two pages of the same block cannot be written simultaneously unless that block is erased first. Such an access characteristic of the NAND flash memory presents a difficulty in its management.
To make a NAND flash memory to work under an existing file system and format (such as FAT16/32, NTFS, EXT2, etc.), the most frequently adopted approach is to maintain an address translation table mapping logical addresses to physical addresses of the NAND flash memory. As such, the NAND flash memory can be simulated into a continuous memory space and, without altering the existing file system and format, the NAND flash memory can be treated as, for example, a hard disk. This approach is referred to as the NAND flash translation layer.
As the capacity of the NAND flash memory is increased, the NAND flash translation layer uses a block-level mapping mechanism to reduce RAM (Random Access Memory) space required to maintain the address translation table. However, the block-level mapping is inefficient in mapping logical addresses to the physical flash memory addresses. This is because the flash memory is read or written in units of pages but to obtain a new page address, under the block-level mapping, the pages in a block has to be searched which takes some time. As such, the efficiency and speed in reading and writing the NAND flash memory are affected.
In the prior arts, for example, Taiwan Patent Publication Nos. I253564 and I249670 teach a typical flash memory address translation technique, a management method of good and bad blocks, and a method and technique for sequentially writing data into the flash memory from virtual blocks. These teachings also require mapping logical addresses to physical flash memory addresses in accessing data, and suffer the same inefficient problem.